AI chips keep getting more powerful, but getting electricity into them is becoming the real bottleneck. Infineon Technologies has introduced a new dual-phase smart power stage family, the TDA235E5 and TDA235E0, that claims a benchmark power density of more than 2 A/mm2 for next-generation AI accelerator power delivery. The tiny 6 x 6 mm devices can handle up to 300 A peak current, support both lateral and vertical power layouts, and are designed with liquid cooling in mind. This article explains what Infineon announced, what a smart power stage actually does, and why vertical power delivery is becoming essential as AI racks push toward hundreds of kilowatts.
What Infineon Announced on September 7, 2026
On September 7, 2026, Infineon Technologies announced the TDA235E5 and TDA235E0, a dual-phase smart power stage family aimed at next-generation AI xPU accelerators, server CPUs, and vertical power delivery modules. Each device integrates OptiMOS 6 MOSFETs with a dual-phase driver IC in a compact 6 x 6 x 0.8 mm package.
The headline figures from the official Infineon technology announcement are:
- Power density exceeding 2 A/mm2, which Infineon describes as a new benchmark for power stages in high-current AI processor applications.
- Up to 300 A peak current and 120 A total design current (TDC) per device.
- Support for both lateral and vertical power delivery configurations.
- Low thermal impedance from junction to top side, designed for efficient integration with liquid cooling.
- Compatibility with Infineon digital multiphase controllers for scalable multi-rail architectures.
Engineering samples of both parts are now available for customer evaluation. Infineon positions the family inside its end-to-end AI server power chain, spanning grid interface to processor core rails and combining silicon, silicon carbide, and gallium nitride technologies.
What Is a Smart Power Stage?
A smart power stage is the last link in the chain that feeds an AI chip. Server power arrives at relatively high voltage, then steps down through several stages until it reaches the roughly 1 volt or less that a processor core needs, at hundreds of amps. The power stage is the compact module that performs that final conversion right next to the chip, combining power transistors (MOSFETs) and the driver circuitry that switches them.
Its job matters because every milliohm of resistance and every millimeter of distance in that final stretch wastes energy as heat. As one industry analysis of voltage regulation moving into the processor package explains, the farther the regulator sits from the chip, the higher the resistance, inductance, and losses. A dual-phase design like Infineon’s splits the current across two phases inside one package, which spreads heat, reduces ripple, and lets designers scale up by paralleling more phases for different rails.
Why Power Density Is Now the Bottleneck for AI Accelerators
AI accelerator power demand has exploded. A standard enterprise rack once drew 7 to 12 kW. An NVIDIA H100 training rack draws 40 to 50 kW, and the GB200 NVL72 rack-scale system draws around 120 kW. Per-GPU power has climbed from 700 W for the H100 to 1,000 W or more for Blackwell-class GPUs, with future devices projected toward 1,400 to 1,800 W. Infineon itself notes that next-generation processors may need 2 to 4 kW per GPU, pushing rack power toward 1 MW and beyond by 2030.
That creates a physical problem. Around a large AI processor, there is only so much board space for the thirty or more regulator phases a training chip can require. Power components must deliver more current from a smaller footprint, which is exactly what the 2 A/mm2 figure measures: how many amps each square millimeter of package can support. Higher density frees board space, shortens power paths, and cuts the copper losses that otherwise waste tens of watts per processor.
Lateral vs. Vertical Power Delivery Explained
Most servers today use lateral (horizontal) power delivery: regulator modules sit beside the processor on the motherboard, and current travels sideways through board traces, up into the chip, and back. It works, but long traces mean higher resistance and inductance, and losses grow with the square of the current.
Vertical power delivery moves conversion underneath or directly against the processor package, dramatically shortening the current loop. Test data published by power module maker Vicor shows the scale of the prize: moving one core power module from lateral to vertical placement cut power distribution impedance by a factor of six, from 60 to 11 micro-ohms, and cut board copper losses from 60 W to 11 W at a 1,000 A load. Across a 64-accelerator rack, that single change saves roughly 3.2 kW of continuous waste heat, according to the Vicor analysis of vertical power delivery efficiency.
| Feature | Lateral power delivery | Vertical power delivery |
|---|---|---|
| Module placement | Beside the processor on the board | Underneath or against the processor package |
| Current path length | Long, through board traces | Short, near-direct into the chip |
| Distribution impedance | Higher (around 60 micro-ohms in cited test) | Lower (around 11 micro-ohms in cited test) |
| Copper losses at 1,000 A | Around 60 W per accelerator module | Around 11 W per accelerator module |
| Design maturity | Established, flexible layout | Emerging, needs dense modules like Infineon’s |
Infineon’s new stages support both layouts, which matters because the industry is mid-transition. Designers can use the parts in today’s lateral boards while preparing vertical module designs for advanced AI processor packages, without changing the power stage family.
Liquid Cooling and Thermal Design
As socket power climbs past 1 kW, air cooling runs out of headroom. Rack densities of 40 to 120 kW have already made liquid cooling standard for AI builds, and projected 250 kW to 1 MW racks will demand it universally. Infineon highlights the top-side thermal path of the TDA235E5 and TDA235E0: low junction-to-top impedance lets heat flow efficiently into cold plates or liquid-cooled heatsinks mounted above the package.
This is a practical detail with big consequences. If a power stage cannot shed heat upward into the cooling loop, its current rating drops and the whole processor must throttle. Designing for top-side cooling from the start lets hyperscalers pack more current into the same footprint without creating hot spots that air alone cannot remove.
Ecosystem, Compatibility, and Availability
Infineon pairs the new stages with its digital multiphase controllers, enabling flexible multi-rail designs where different voltage domains of an AI accelerator (core, memory, auxiliary) each get tailored phases. That scalability shortens deployment time in fast-moving server platforms where each accelerator generation changes rail counts and current targets.
The broader context is Infineon’s push across the full AI server power chain, from grid and rack distribution down to core rails, using silicon alongside silicon carbide and gallium nitride where each fits best. The company calls data center power one of the semiconductor industry’s fastest-growing demand segments, and this launch targets the component level where density pressure is most acute.
For now, both devices are at the engineering sample stage for customer evaluation. Infineon has not disclosed production timing, volume pricing, or the detailed differences between the TDA235E5 and TDA235E0 variants, so server designers will watch for datasheets and qualification updates before planning volume builds.
Frequently Asked Questions
What are AI accelerators used for?
AI accelerators are specialized chips that speed up machine learning workloads such as training large models and running inference. Examples include data center GPUs, Google TPUs, AWS Trainium, and Microsoft Maia. They handle the massive parallel math that general-purpose CPUs do too slowly, which is why they dominate AI data centers.
Is an AI accelerator the same as a GPU?
Not exactly. A GPU is one type of AI accelerator and currently the most common. The broader category also includes TPUs, NPUs, and custom ASICs designed only for AI math. All of them share the same power challenge: very high current at very low voltage, delivered with minimal loss.
How does an AI accelerator work?
An accelerator breaks neural network math into thousands of parallel operations executed across many cores, fed by high-bandwidth memory stacked nearby. That parallelism delivers huge throughput but draws enormous current in bursts, so the power delivery network must respond in microseconds without letting voltage droop.
How much electricity is AI actually using?
United States data centers consumed roughly 176 TWh in 2023, about 4.4 percent of national electricity, rising to around 183 TWh in 2024, according to Department of Energy figures. A single AI rack can now draw 40 to 132 kW versus 5 to 15 kW for a conventional rack, which is why efficiency gains in components like power stages compound into megawatts of savings at data center scale. For related coverage, see our analysis of Microsoft Maia power and vertical integration and our explainer on AI accelerators from TPU v7 to Maia 200.
What This Launch Signals
Infineon’s 2 A/mm2 claim is a component-level milestone, but its significance is systemic. AI infrastructure is shifting toward vertical power, liquid cooling, and kilowatt-class sockets, and every watt wasted in delivery becomes heat the data center must pump out again. Denser, cooler-running power stages buy headroom that architects can spend on compute instead of copper. If samples validate in customer systems, expect vertical-ready power stages to become standard equipment in the next wave of AI accelerator platforms.
