A South Korean semiconductor packaging company has unveiled a novel metallization technology that could solve one of the most stubborn manufacturing challenges in next-generation chip packaging. According to TheElec, Kools announced on August 21, 2026, that it will present its Self-Propagating Electrode Architecture (SPEA) at an upcoming advanced packaging seminar in Suwon, South Korea, offering a new approach to filling microscopic holes in glass substrates with copper.
The technology arrives at a critical moment. As artificial intelligence accelerators grow larger and more complex, the semiconductor industry is racing to develop glass-based substrates that can replace traditional organic and silicon materials. The demand for advanced packaging capacity has never been higher, and glass substrate plating innovations like SPEA could help bridge the gap. Kools’ SPEA addresses a fundamental bottleneck in that transition: how to reliably fill high-aspect-ratio through-glass vias with metal without creating voids or blocking the via entrance.
What Are Glass Substrates and Why Do They Matter?
Glass substrates are thin panels of specialized glass used as the foundation for advanced semiconductor packaging. Unlike traditional organic substrates made from resin and fiberglass, glass offers superior flatness, lower electrical signal loss, and a coefficient of thermal expansion that can be precisely tuned to match silicon chips.
These properties make glass particularly attractive for AI accelerators and high-performance computing chips that require:
- Higher wiring density to connect multiple chiplets
- Better signal integrity at high frequencies
- Improved thermal management under heavy workloads
- Larger package sizes to accommodate growing chip designs
According to IDTechEx research, glass is gradually moving from a background consumable to the heart of advanced packages
, providing the core substrate, the interposer that links chiplets, and the dielectric that shapes sub-terahertz signals. Intel has publicly demonstrated glass core substrates, while Samsung Electronics and SK Absolics are actively developing their own glass-based solutions.
The Challenge: Metallizing High-Aspect-Ratio Through-Glass Vias
Through-glass vias (TGVs) are microscopic holes that vertically penetrate glass substrates to connect wiring on the top and bottom surfaces. These vias are essential for creating the electrical pathways that allow signals to flow between stacked chips and between chips and the circuit board below.
The difficulty lies in metallizing high-aspect-ratio TGVs, where the via diameter is small relative to the glass thickness. Traditional methods face significant limitations:
Sputtering (Physical Vapor Deposition)
Sputtering uses plasma under vacuum to dislodge metal atoms and deposit them on the glass surface. Because metal atoms travel in relatively straight paths, they struggle to reach the lower portions of deep, narrow vias. This results in non-uniform metal coverage, particularly along the sidewalls near the bottom of the via.
Wet Electroless Plating
This chemical process forms a catalyst on the via’s inner wall and then creates a metal layer through a chemical reaction. If the catalyst does not form uniformly, adhesion between the metal layer and glass weakens in some areas. Exposure to heat or moisture can then lead to interfacial defects such as delamination.
Both methods can produce voids, seams, or blockages at the via entrance, compromising the reliability of the final package. As the semiconductor industry pushes toward finer via geometries and higher aspect ratios, these limitations become increasingly problematic.
Kools’ SPEA Technology: Self-Propagating Electrode Architecture
Kools’ solution involves two complementary technologies that work together to enable reliable, void-free filling of high-aspect-ratio TGVs.
Functional Interface Formation
The first technology addresses the fundamental challenge of metal-to-glass adhesion. Glass has inherently low adhesion to metals, making it difficult to form a uniform metal layer on the via’s inner wall. Kools’ approach first creates a functional interface across the entire inner wall of the via, designed to enable uniform metal deposition regardless of the via’s geometry.
Self-Propagating Electrode Architecture (SPEA)
The second technology is the core innovation. SPEA works by forming an initial electrode at the bottom of the via or in a specific area. As the metal grows from this seed point, the newly reached regions themselves become electrodes, driving further metal deposition. This creates a self-sustaining filling process that sequentially fills the via from the bottom toward the top.
- Reduced blockage at the via entrance, since metal grows upward rather than inward from the sidewalls
- Minimized internal void formation, as the sequential filling process ensures continuous metal deposition
- Improved reliability, with more uniform metal coverage throughout the via
- Compatibility with panel-level packaging (PLP) scale, enabling large-area manufacturing
“Glass core substrates and glass interposers differ in via size and wiring density, but their manufacturing principles are the same,” said Kools CEO Cho Jin-hyun. “We will present a TGV metallization platform that can support PLP-scale large-area panels, rather than an individual via plating process.”
How SPEA Compares to Traditional Methods
The following table summarizes the key differences between Kools’ SPEA technology and conventional TGV metallization approaches:
| Feature | Sputtering (PVD) | Wet Electroless Plating | Kools SPEA |
|---|---|---|---|
| Filling Direction | Conformal (sidewall-in) | Conformal (sidewall-in) | Bottom-up (sequential) |
| High-Aspect-Ratio Capability | Limited (poor sidewall coverage at depth) | Moderate (catalyst uniformity issues) | Excellent (self-propagating growth) |
| Void Formation Risk | High (premature entrance closure) | Moderate (catalyst gaps) | Low (sequential filling) |
| Adhesion Reliability | Moderate | Variable (depends on catalyst) | High (functional interface) |
| Scalability to Panel-Level | Challenging (vacuum process) | Moderate | Designed for PLP scale |
Kools currently holds 118 patent applications related to glass-substrate packaging, covering the entire process from glass-to-metal bonding and continuous functional metallization interfaces to TGV seed formation, metal-ion-storing sidewalls, SPEA, sequential filling, large-area panel power feeding, and redistribution layers (RDLs).
Who’s Leading the Glass Substrate Revolution?
Kools is entering a rapidly evolving competitive landscape where major semiconductor companies and materials suppliers are all investing heavily in glass substrate technology.
Intel
Intel has been an active mover in glass substrate technology. As early as 2023, Intel committed to glass substrates in its advanced packaging roadmap. In January 2026, it debuted the first sample combining EMIB packaging with a glass core substrate at NEPCON Japan, achieving what the company called “No SeWaRe” (no micro-cracks), marking a decisive step toward commercial reality.
Samsung and SK Absolics
Samsung Electronics is exploring glass cores as a potential option alongside its I-Cube and H-Cube packages. Meanwhile, SK Absolics, an affiliate of SKC, has secured preliminary U.S. CHIPS Act support to build a glass-substrate facility in Georgia and is targeting mass production in 2026.
TSMC
TSMC introduced its 310 x 310 mm CoPoS (Chip-on-Panel-on-Substrate) platform in 2025, where glass is used as the interposer. The company has built a pilot production line, with meaningful ramp-up expected in two to three years.
According to TrendForce analysis, glass substrates are expected to begin early commercialization in 2027, move through a ramp-up phase by 2029, and enter full-scale mass production from 2030 onward. NVIDIA and Google are seen as the most likely end customers to drive adoption.
What This Means for AI Chips and Advanced Packaging
The convergence of glass substrate technology and advanced packaging techniques like CoWoS is reshaping how the semiconductor industry approaches AI chip manufacturing. As advanced compute packaging becomes a critical bottleneck for AI supply chains, innovations like Kools’ SPEA become increasingly valuable.
Glass substrates offer several advantages for AI accelerators, as explored in our analysis of how TSMC, Intel, and Samsung are solving the CoWoS bottleneck:
- Better heat and warpage resistance compared to organic substrates
- Finer redistribution layer (RDL) geometries, enabling sub-2-micron features
- Support for larger package sizes (60 to 80 mm multi-chiplet packages)
- Integration of high-bandwidth memory (HBM) stacks
- Potential for co-packaged optics (CPO) using glass transparency for optical waveguides
The economic case is also compelling. As TSMC, Intel, and Samsung compete to solve the CoWoS bottleneck, glass substrates present a path to reducing costs. Current glass substrate technology carries a 2-3x cost premium over organic alternatives, but industry roadmaps project a 40-60% cost reduction by 2030 as yields improve from the current 75-85% range. This mirrors the broader cost dynamics reshaping AI compute infrastructure.
Kools’ SPEA technology directly addresses one of the key yield-limiting steps in glass substrate manufacturing. By enabling reliable, void-free filling of high-aspect-ratio TGVs at panel-level scale, it could accelerate the timeline for commercial adoption of glass-based packaging.
Frequently Asked Questions
What is a glass substrate used for?
Glass substrates serve as the foundational platform for advanced semiconductor packaging. They replace traditional organic substrates (made from resin and fiberglass) or silicon interposers to connect multiple chips, chiplets, and memory stacks in a single package. Glass substrates are particularly important for AI accelerators, high-performance computing, 5G/6G infrastructure, and autonomous vehicle processors where high wiring density, signal integrity, and thermal stability are critical.
What is the most recent technology in glass substrate manufacturing?
The most recent breakthroughs include Kools’ Self-Propagating Electrode Architecture (SPEA) for through-glass via metallization, Intel’s demonstration of micro-crack-free glass core substrates using EMIB packaging, and TSMC’s CoPoS platform using glass interposers. The industry is also advancing laser-induced deep etching (LIDE) for creating vias as small as 6 micrometers with 15:1 aspect ratios, and developing sub-2-micron redistribution layer geometries.
Who manufactures glass substrates for semiconductors?
Major players include Intel (developing glass core substrates in-house), SK Absolics (a subsidiary of SKC, building a facility in Georgia with U.S. CHIPS Act support), Samsung Electronics (exploring glass cores for advanced packages), and TSMC (developing glass interposer solutions). Materials suppliers like SCHOTT and AGC are also aligning their portfolios around low-coefficient-of-thermal-expansion glass for packaging applications. Kools, the company behind SPEA, holds 118 patent applications in glass-substrate packaging technology.
What is electroplating glass in semiconductor manufacturing?
Electroplating glass refers to the process of depositing a metal layer (typically copper) onto glass surfaces and inside through-glass vias (TGVs) to create electrical connections. This is a critical step in glass substrate manufacturing because glass does not naturally adhere well to metals. Traditional methods include sputtering (physical vapor deposition) and wet electroless plating, while newer approaches like Kools’ SPEA use bottom-up filling to achieve more reliable, void-free metallization.
How does glass compare to silicon for semiconductor substrates?
Glass offers several advantages over silicon as a substrate material: its coefficient of thermal expansion can be tailored to match silicon chips, its signal loss is an order of magnitude lower than silicon at high frequencies (40 GHz), and large-panel processing from the LCD industry enables cost-effective manufacturing of substrates up to half a meter on a side. However, silicon interposers currently provide finer redistribution with true vertical interconnection via through-silicon vias (TSVs), and both materials carry high costs that must be proven at system scale before widespread adoption.
Conclusion: A Korean Innovation Shaping Global Chip Packaging
Kools’ SPEA technology represents a significant contribution from South Korea’s semiconductor ecosystem to the global challenge of next-generation chip packaging. By solving the fundamental metallization bottleneck for high-aspect-ratio through-glass vias, the technology could accelerate the timeline for glass substrate adoption across the industry.
The announcement comes at a pivotal moment. With Intel, Samsung, TSMC, and SK Absolics all investing billions in glass substrate infrastructure, and with AI chip demand continuing to outpace packaging capacity, manufacturing innovations that improve yield and reliability will be critical to meeting the industry’s ambitious 2027-2030 commercialization targets.
Kools CEO Cho Jin-hyun will present the technology in detail at the “CPO and Advanced Packaging: Key to AI Semiconductor Performance Innovation” seminar at Suwon Convention Center on August 27, 2026. The presentation, titled “New Glass Core Technology for Panel-Level Packaging (PLP)-Scale Large-Area Applications,” is expected to provide deeper technical insights into how SPEA can support the transition from wafer-level to panel-level manufacturing.
As the semiconductor industry continues its push toward larger, more complex AI accelerators, innovations like SPEA demonstrate that breakthroughs in manufacturing processes are just as important as advances in chip design. The race to perfect glass substrate technology is well underway, and Korean companies like Kools are helping to define its trajectory.
