Alibaba’s XuanTie C950, a 64-core RISC-V processor built on TSMC’s 5nm process, just demonstrated something no chip using the open-source instruction set has ever done before: it ran a 27-billion-parameter language model entirely on the CPU, with no GPU, no emulation layer, and no translation overhead. The implications stretch far beyond a single benchmark result, touching on China’s semiconductor sovereignty strategy, the future of the RISC-V architecture, and how the Alibaba RISC-V chip stack could reshape AI deployment.
The Qwen 3.8 27B model, released under an open-source license on August 14, 2026, achieved 30 tokens per second on the C950 with a time-to-first-token of 1.9 seconds. For context, running a 27-billion-parameter model conventionally requires 16 to 24 gigabytes of dedicated GPU memory. The C950 completes the same inference task using its CPU cores and integrated AI acceleration engines alone.
Inside the XuanTie C950 Architecture
The XuanTie C950 is a server-grade 64-bit RISC-V processor that Alibaba’s DAMO Academy unveiled at the 2026 RISC-V Ecosystem Conference in Shanghai. Manufactured on TSMC’s 5nm process node (with a 7nm variant reportedly produced by SMIC as a fallback), the chip packs 64 compute cores organized into eight clusters of eight cores each, interconnected via high-speed AMBA CHI fabrics.
Key specifications include:
- Clock speed: up to 3.2 GHz
- Decode width: 8 instructions per cycle
- Pipeline: 16 stages, out-of-order execution window exceeding 1,000 instructions
- Cache: L1 per core, configurable L2, optional shared L3
- Benchmark: SPECint2006 score above 70 (a new RISC-V world record)
- Performance improvement: 3x over predecessor C920, 4x memory bandwidth increase
What distinguishes the C950 from a conventional server CPU is its integrated AI acceleration. Alibaba embedded two purpose-built engines directly into the chip: a Vector Acceleration Engine for parallel data operations and a Matrix Acceleration Engine for the tensor computations that dominate transformer-based inference. These are not bolted-on co-processors. They share unified addressing with the CPU cores, creating tight coupling between general-purpose compute and AI-specific workloads.
At the heart of the AI subsystem sits the XuanTie Tensor Processing Engine (TPE), which delivers 8 TOPS (tera operations per second) per unit and supports data formats critical for modern AI: FP16, FP8, INT4, and microscaling formats like MXFP8, MXFP4, and RVFP4. The chip also implements the RISC-V Attached Matrix Extension (AME), a proprietary ISA extension that lets the matrix engine execute tensor operations directly through the CPU’s instruction pipeline.
The C950 is fully compliant with the RVA23 profile, the latest RISC-V server platform specification. RVA23 mandates vector extensions (RVV 1.0), hypervisor support, and native handling of FP8 and BF16 data types, all essential for generative AI workloads. Google researcher Laurie Kirk noted her surprise at how quickly Alibaba adopted RVA23.1, a minor update proposed in August 2025, signaling the company’s aggressive development pace.
On the C950, the SPECint2006 score of over 70 points per core at 3.2 GHz translates to roughly 22 points per GHz. For comparison, the previous-generation C930 managed around 15 points per GHz. Independent analysis places the C950’s single-thread performance nearly on par with Apple’s M1 chip, which launched in late 2020.
The Qwen 3.8 27B Milestone
The demonstration that matters most is this: in August 2026, Alibaba ran its Qwen 3.8 27B model natively on a 64-core C950 configuration. The results: 30+ tokens per second decode speed, with a time-to-first-token of 1.9 seconds. This marks the first time a RISC-V processor has driven a 27-billion-parameter language model directly, without relying on a GPU, an emulation layer, or ISA translation software.
The Qwen 3.8 27B model itself is a significant release. Launched on August 14, 2026, under the Apache 2.0 license, it is a dense, multimodal, vision-language model with 27.78 billion parameters. The architecture uses a hybrid design: 48 Gated DeltaNet layers for linear attention and 16 full-attention layers, totaling 64 decoder layers with a hidden dimension of 5,120. It accepts text, image, and video input, with a native context window of 262,144 tokens extensible to 1 million via YaRN scaling.
On standard benchmarks, the 27B model punches well above its weight class:
| Benchmark | Qwen 3.8 27B | Claude Opus 4.6 Max | Qwen 3.6 27B |
|---|---|---|---|
| SWE-bench Pro | 61.7 | 53.4 | 53.5 |
| Terminal-Bench 2.1 | 73.0 | 78.2 | 63.4 |
| LiveCodeBench v6 | 90.3 | 88.8 | 83.9 |
| GPQA Diamond | 89.2 | 91.3 | 87.8 |
| OSWorld-Verified | 84.3 | 72.7 | 63.9 |
| AndroidWorld | 81.9 | 62.0 | 70.3 |
| DeepSWE 1.1 | 42.2 | — | 13.3 |
The model outperforms Claude Opus 4.6 Max on SWE-bench Pro, a real-world software engineering benchmark, and dominates on computer-use and mobile-agent tasks. At 4-bit quantization, the entire model fits in roughly 17 GB of memory, meaning it can run on a single consumer GPU like an RTX 4090 or even a high-end laptop with 24 GB of unified memory.
On the C950, Alibaba also tested the much larger Qwen 3.8 2.4T-A95B model, which achieved 7.2 tokens per second with an 8.5-second time-to-first-token, demonstrating that the chip can handle models with hundreds of billions of parameters, though at reduced throughput.
How It Compares: RISC-V vs. ARM vs. x86
The C950 arrives at a pivotal moment for RISC-V. In 2026, the open-source instruction set architecture crossed the 25% global market share threshold across application processors, microcontrollers, and AI accelerators. For the first time in 25 years, the x86 and ARM duopoly has become a three-way contest. The SHD Group projects 36 billion RISC-V device shipments by 2031, with a market value exceeding $300 billion.
The three architectures occupy overlapping but distinct positions:
- x86 (Intel, AMD): Still holds the crown for peak single-thread performance in desktops and servers. Effectively a duopoly that cannot be licensed for custom chip designs.
- ARM (Arm Holdings): Dominates mobile efficiency and has become a serious datacenter contender through Neoverse. Licensed architecture with per-unit royalties and controlled access.
- RISC-V: Open standard with no royalties and no gatekeeper. Built for extension: the base ISA is small, and designers add standard or custom extensions for AI, DSP, cryptography, or domain-specific workloads.
Recent RISC-V designs have closed the performance gap with ARM. The Tenstorrent Ascalon-X core achieves roughly 22 SPECint2006 points per GHz, placing it in direct parity with AMD’s Zen 5 and ARM’s Neoverse V3. Studies indicate that RISC-V designs deliver 30 to 40% better power-performance-area metrics than comparable ARM configurations for cloud-native workloads. ARM still maintains advantages in ecosystem maturity and raw inference performance for large networks, but RISC-V’s flexibility and zero licensing cost make it increasingly attractive for custom AI silicon.
The C950’s SPECint2006 score of over 70 represents a 3x leap over its predecessor, the C920, and sets a new bar for what RISC-V can achieve in server-class computing. While it does not match the latest x86 or ARM flagship processors in raw throughput, it demonstrates that RISC-V has entered the same performance tier as architectures from five to six years ago, a timeline that is compressing rapidly with each generation.
The Geopolitical Play: Why RISC-V Matters for China
Alibaba’s decision to build the C950 on RISC-V is inseparable from geopolitics. The United States has imposed increasingly strict export controls on advanced semiconductor technology destined for China, restricting access to cutting-edge AI accelerators from NVIDIA and AMD, and limiting Chinese access to advanced chipmaking equipment from ASML, Applied Materials, and Lam Research.
RISC-V offers a way around these constraints. As an open-standard ISA governed by RISC-V International, a Swiss-headquartered organization, it has no royalties and no licensing gatekeeper. Any company can implement the architecture, modify it, and add custom extensions without asking permission. This makes it qualitatively different from x86 (controlled by Intel and AMD) and ARM (which licenses its ISA and core designs under commercial terms that can be restricted by export policy).
China’s semiconductor localization drive has accelerated since 2022. The Chinese government has reportedly directed domestic enterprises to acquire local chips and equipment, even when those alternatives are less advanced than foreign options. China’s $70 billion chip subsidy program is funding the development of domestic alternatives across the supply chain. RISC-V has become a central pillar of this strategy.
The C950’s manufacturing approach reflects a dual-track resilience strategy. The chip is verified on TSMC’s 5nm process for maximum performance, but industry reports indicate that a domestic Chinese partner, widely believed to be SMIC, is also producing the chip using 7nm technology. This parallel development means Alibaba is not wholly dependent on Taiwanese foundries, hedging against potential further restrictions on TSMC’s ability to manufacture chips for Chinese customers.
The strategic significance is not lost on analysts. As CNBC noted, the XuanTie CPUs can be tailored to specific inference patterns, allowing customers to customize them for particular workloads, a capability that proprietary architectures from Intel or ARM do not readily offer.
Alibaba’s Vertical Integration Strategy
The C950 and Qwen 3.8 pairing reveals a strategy that closely mirrors NVIDIA’s well-established playbook: control the silicon, the software framework, and the deployment platform. But Alibaba’s version has a distinct twist, rooted in the open nature of RISC-V.
NVIDIA’s dominance rests on CUDA, its proprietary software ecosystem that locks developers into NVIDIA hardware. Alibaba’s approach is different. By building on RISC-V, the company retains the ability to customize the instruction set and acceleration engines for its own models while keeping the base architecture open. The C950 is optimized from the ground up for Qwen models and DeepSeek V3, with hardware acceleration engines designed to execute their core operations natively. But the open ISA means partners and customers can also deploy other software stacks on the same silicon.
The vertical integration compresses the optimization loop. Model operators can be redesigned around hardware characteristics, while future chip generations can incorporate instructions and data paths informed by production telemetry from the Qwen deployment. This feedback cycle between hardware and software teams, operating under the same corporate roof, is a structural advantage that few competitors outside NVIDIA can replicate.
Alibaba has also paired the C950 with specialized AI accelerators from domestic partners, including the Jiangyuan Tech D20 and the Rockchip RK1828. These companion chips handle highly parallel tensor operations while the C950 manages orchestration, retrieval, pre- and post-processing, and latency-sensitive agentic workloads. The result is a modular inference stack built entirely from Chinese-designed silicon.
T-Head, Alibaba’s chip subsidiary, has shipped over 470,000 AI chips to date, with annualized revenue approaching $1.45 billion. The XuanTie processor family powers nearly 1,000 devices across servers, robotics, and electric vehicles. Speculation about a T-Head IPO has grown as the division’s commercial scale has expanded.
What This Means for AI Deployment
The ability to run a 27-billion-parameter model at 30 tokens per second on a CPU, without any GPU, shifts the economics of AI inference. Traditional GPU-based setups require 16 to 24 GB of dedicated VRAM, substantial power budgets, and expensive hardware that remains in short supply globally. The C950 handles the same workload using its CPU cores and on-chip acceleration engines, opening deployment scenarios that GPUs cannot easily serve.
Edge inference is the most immediate opportunity. Factories, retail environments, autonomous vehicles, and robotics platforms often lack the power, cooling, or physical space for discrete GPU hardware. A C950-based system can run LLM inference alongside standard cloud workloads like MySQL, Redis, and Nginx on the same silicon, eliminating the need for separate GPU-accelerated inference servers.
Private inference is another compelling use case. Organizations that want to run AI models locally, without sending data to external APIs or cloud services, can deploy Qwen 3.8 27B on C950 hardware. The open-source model weights (Apache 2.0 license) combined with open-architecture silicon create a fully transparent stack from model to metal.
Cost and energy efficiency improve substantially. GPU inference for a 27B model typically consumes hundreds of watts per accelerator. The C950’s CPU-centric approach, with tightly integrated acceleration engines, delivers inference at a fraction of the power envelope. For cloud providers running mixed workloads, the ability to serve both general-purpose computing and AI inference on the same processor type simplifies infrastructure and reduces hardware diversity.
There are tradeoffs. The 30 tokens per second throughput on the C950 is significantly lower than what a high-end GPU like an NVIDIA H100 can achieve on the same model. The C950 runs a single inference thread per socket, making it better suited for edge deployment and private inference than for high-concurrency public API serving. But for latency-sensitive agentic workloads, interactive applications, and scenarios where GPU hardware is unavailable or impractical, the C950 offers a viable and increasingly competitive alternative.
Frequently Asked Questions
Who manufactures the XuanTie C950?
The C950 is designed by Alibaba’s T-Head semiconductor division and manufactured on TSMC’s 5nm process. Industry reports indicate that a 7nm variant is also being produced by SMIC, a Chinese domestic foundry, as a sanctions-resilient alternative.
How does RISC-V compare to ARM for AI workloads?
RISC-V offers up to 4x lower power consumption and enables custom AI acceleration without licensing constraints, making it well-suited for power-constrained deployments. ARM maintains advantages in ecosystem maturity and raw inference performance for large networks, delivering up to 15x faster inference for complex models through mature toolchains. The choice depends on whether customization and sovereignty or ecosystem readiness matter more for a given deployment.
What can the C950 run besides Qwen 3.8 27B?
The C950 natively supports multiple large language models, including Qwen3, DeepSeek V3, and the much larger Qwen 3.8 2.4T-A95B, which achieves 7.2 tokens per second on the chip. It also handles standard cloud-native workloads like MySQL, Redis, Nginx, and OpenSSL, making it a general-purpose server processor with integrated AI capabilities.
Is the XuanTie C950 commercially available?
Alibaba announced the C950 in March 2026 at the RISC-V Ecosystem Conference in Shanghai. As of August 2026, the company has not disclosed specific commercial availability dates or pricing. T-Head has shipped over 470,000 AI chips cumulatively, and the XuanTie processor family is already deployed in nearly 1,000 devices, suggesting that broader commercial rollout is likely in the near term.
Why does Alibaba use RISC-V instead of ARM or x86?
RISC-V is an open-standard instruction set architecture with no royalties and no licensing gatekeeper. This allows Alibaba to customize the chip for specific AI workloads, avoid dependency on Western intellectual property that could be restricted by export controls, and build a vertically integrated hardware-software stack that no foreign government can throttle. ARM and x86 architectures come with licensing fees and access restrictions that RISC-V does not impose.
