Samsung’s next-generation HBM4E memory reportedly cleared qualification testing with Nvidia and several major data center customers at the end of September. The news came from a Hankyung report published on October 7.
The result puts Samsung back in position to supply high-bandwidth memory for Nvidia’s Rubin Ultra accelerators. It also lands about a year after the company’s HBM3E failed to meet Nvidia’s requirements. Qualification is a technical milestone, not a signed supply contract, and neither company has confirmed the report.
What Just Happened With Samsung’s HBM4E
Hankyung reported that Samsung’s memory division finished qualification testing of its 12-high HBM4E at the end of September. The testing involved Nvidia and several hyperscale operators. Trade coverage of the report said the qualification applies to Nvidia’s next-generation Rubin Ultra accelerator family.
Samsung began shipping the industry’s first 12-layer HBM4E samples in May, and the company has been open about the product’s direction since then. But when Hankyung asked about the qualification, Samsung said it could not confirm whether the testing had been completed. Nvidia has not commented.
Qualification is the stage where a memory maker proves a part meets a customer’s requirements. Those requirements cover electrical behavior, heat, reliability, and compatibility. Passing means the part has moved from a promising sample to a product that can be considered for commercial supply. It is also the step that has given Samsung the most trouble in the AI era.
Qualification Is Not the Same as a Supply Deal
Passing qualification does not confirm volumes, contract value, or delivery timelines. Samsung does not publish customer qualification schedules. Its own HBM documentation states that specific timelines for HBM customer qualification have not been publicly disclosed.
The report also relies on unnamed sources. The practical test will come over the next two quarters, through sample volume, wafer allocation, and any customer confirmation that follows.
A Comeback After the HBM3E Miss
The HBM3E failure explains why this qualification matters so much. Samsung’s HBM3E did not meet Nvidia’s requirements. Nvidia used Samsung for GDDR7 instead and left the company out of HBM3E supply. That allowed SK hynix and Micron to strengthen their positions in AI memory.
Market estimates put Samsung at roughly 17 percent of global HBM sales. Micron sits near 21 percent, and SK hynix leads a segment it began investing in back in 2017.
Catching up at the HBM4 generation has been Samsung’s clearest strategic priority. HBM4E is where that work is finally being validated by the customer that matters most.
What Is HBM4E?
HBM stands for high bandwidth memory. Instead of placing memory chips next to a processor, HBM stacks them vertically and mounts the stack immediately beside the accelerator.
That layout lets an AI chip pull in the weights, activations, and cached context it needs to keep its compute units busy. The shorter and wider the connection, the less time the chip spends waiting.
HBM4E is the enhanced generation that follows HBM4, built on 1c-class DRAM with a 4-nanometer logic base die.
How a Stack of Memory Works
A modern HBM device is a small, nearly square package. It is usually one to two square centimeters in area and about a millimeter thick, according to Samsung’s technical documentation.
Inside, ultra-thin DRAM dies are stacked as many as 16 layers deep. Through-silicon vias, the vertical copper connections, carry data through the stack. A logic base die sits beneath it and manages the interface to the accelerator. The whole assembly then rests on a silicon interposer.
More layers mean more capacity and bandwidth. They also mean more heat and more manufacturing difficulty. That is why stacking and packaging have become the real bottleneck in AI hardware, not the memory cells themselves.
The Specs That Matter
Samsung’s published HBM4E figures are:
- Up to 64 GB of capacity per stack in a 16-high configuration
- Up to 4 TB/s of bandwidth per stack at 16 Gbps per pin
- 3.6 TB/s at 14 Gbps per pin
- A 2,048-bit interface, double the width of HBM3 and HBM3E
- More than 20 percent faster per pin than HBM4
- Roughly 16 percent better energy efficiency than HBM4, with improved thermal resistance
Samsung announced the sample shipment in May and called it an industry first. The 12-high, 48 GB version is the first to ship, and Samsung says it carries more than 30 percent more capacity than HBM4’s 36 GB. Customer requirements are expected to add 8-high 32 GB and 16-high 64 GB stacks later.
HBM4E vs HBM3E: What Actually Changed
Samsung’s published specifications show how far the stack has moved in two generations:
| Generation | Bandwidth per stack | Speed per pin | Interface | Capacity per stack |
|---|---|---|---|---|
| HBM3 | 819 GB/s | 6.4 Gbps | 1,024-bit | 16 to 24 GB |
| HBM3E | 1,180 GB/s | 9.2 Gbps | 1,024-bit | 24 to 36 GB |
| HBM4 | Up to 3,300 GB/s | 13 Gbps | 2,048-bit | 36 GB |
| HBM4E | Up to 4,000 GB/s | 16 Gbps | 2,048-bit | Up to 64 GB |
The generational jump is not incremental. HBM4E roughly triples bandwidth per stack, doubles the interface width, and nearly doubles capacity.
That widening answers a change in AI workloads. Models with long context windows and mixture-of-experts routing move far more data through memory than the workloads HBM3E was designed for. Inference at scale now hits the same data-movement limits that training did.
Why AI Chips Are Starved for Memory
The industry calls this the memory wall. Compute units can process data faster than memory can deliver it. As a result, accelerators sit idle while they wait.
The energy math is just as lopsided. Moving a single bit on and off a chip can cost many times more energy than the operation that eventually uses it. HBM exists to shorten that trip. That is why bandwidth per stack helps decide how fast a data center can serve a model.
Bandwidth is measured across a whole accelerator, not a single stack. Nvidia’s GPU designs use about a dozen HBM stacks each, so per-stack gains multiply quickly.
In our coverage of OpenAI’s Jalapeño chip, HBM4 delivered 15.4 TB/s of aggregate memory bandwidth at 10 Gbps per pin. It also set a new benchmark for bandwidth per watt.
That is the standard HBM4E will be measured against: not just faster memory, but faster memory that spends less energy per bit moved. For a wider look at how accelerators trade off compute, memory, and power, see our explainer on TPU v7, Trainium3, and Maia 200.
The Base Die: When Memory Starts to Compute
The most consequential change in this generation is not the bandwidth figure. It is the base die.
In earlier HBM, the bottom die was a fixed buffer circuit defined by the JEDEC standard. HBM4 and HBM4E replace it with a logic die that can be customized for a customer. Samsung has reportedly allocated half of its 4 nm SF4 foundry capacity to building HBM4E base dies.
Nvidia’s interest in a custom variant points the same way. Press reports describe it as NVHBM, with roughly 30 percent more bandwidth than standard HBM4E. The idea is memory that is co-designed with the accelerator rather than bought off a shelf.
The shift matters because the base die handles power delivery, testing, and the high-speed interface. It also gives designers room to move some functions closer to where data is stored. That is a step toward the near-memory computing researchers have pursued for years. If the trend continues, HBM stops being a passive component and becomes part of the compute system itself.
The Memory Shortage Behind the Headlines
HBM4E is arriving into the tightest memory market in years. That is not a coincidence.
HBM uses the same fabs and wafers as conventional DRAM, but it consumes far more of them. A CSIS analysis published in September estimates that HBM needs roughly four times the cleanroom capacity per gigabyte compared with standard DRAM. Other estimates put HBM’s wafer use at about three times that of DDR5 for equivalent bits.
This is the mechanism behind the squeeze that HBM is quietly putting on consumer RAM supplies. Every stack of HBM4E that leaves a fab is capacity that does not go into a laptop, a phone, or a car.
The effects are already showing up in prices:
- DDR4 prices rose 700 to 800 percent between early 2025 and late 2026, according to CSIS
- TrendForce expects server DRAM contract prices to climb roughly 270 percent across 2026, with HBM contract prices up a further 70 to 140 percent in 2027
- Data centers are projected to consume around 70 percent of all memory devices produced in 2026
- Average smartphone prices are forecast to rise 14 percent in 2026 to a record $523
- PC configurations with 128 GB of memory increased in price by $575 to $765
- Micron says it can supply only about 50 to 66 percent of key customers’ requirements, and its chief executive expects conditions to be “much tighter in calendar 2027 and 2028 than they were in 2026”
Against that backdrop, a new generation of HBM is not simply a faster part. It is a reallocation of scarce manufacturing capacity toward the highest-margin buyer. The timeline for relief is measured in years, not months.
Who Is Making HBM4 and HBM4E Chips?
Three companies control almost all of the market. Micron, Samsung, and SK hynix accounted for 90.5 percent of global DRAM sales in the fourth quarter of 2025, according to TrendForce data cited by CSIS.
Each is taking a different route into the HBM4 generation:
- SK hynix leads the segment and has moved aggressively on advanced packaging, including the PT7 plant in Cheongju, a $12.85 billion bet on the assembly step that turns DRAM dies into finished HBM stacks. It began shipping its own 12-layer HBM4E samples in June, with up to 16 Gbps per pin and, the company says, more than 20 percent better energy efficiency than HBM4.
- Micron is leaning on hybrid bonding, which joins dies copper-to-copper without solder; CSIS cites a roughly 30 percent reduction in power consumption relative to competing designs. It ships 36 GB 12-high HBM4 and has sampled 48 GB 16-high parts.
- Samsung is staking its claim on process technology, and as of this month it holds HBM4E qualification for Nvidia’s next accelerators. It has also signed an HBM4 memorandum with AMD, spreading its bets across customers.
Nvidia itself buys from more than one supplier. Earlier reports said the Vera Rubin platform would use SK hynix and Samsung HBM4 without Micron. That shows how quickly qualification lists shift, and why HBM4E matters well beyond Samsung’s own roadmap.
What Comes After HBM4E
The next steps are already visible. Sixteen-high stacks paired with hybrid bonding will push capacity and bandwidth higher while shrinking the interconnect pitch. HBM5 is expected to arrive alongside the Rubin-generation accelerators. Glass substrates are being explored to carry the wider 2,048-bit interface without warping silicon interposers.
None of it arrives quickly. A new memory fab costs roughly $15 to $20 billion and takes two to three years or more to build. That is why the shortage is expected to persist through 2027, and possibly into 2028, even with the investment wave now underway.
Whether any of this reaches ordinary devices is the open question. HBM is built for data center accelerators, and the shortage is already making consumer hardware more expensive. The likeliest path to the edge is not raw HBM in a phone. It is the packaging and base-die techniques it is forcing into the mainstream, from hybrid bonding to advanced substrates.
The Bottom Line
Samsung’s HBM4E qualification is best read as a signal rather than a trophy. It restores Samsung to Nvidia’s qualification list after the HBM3E stumble. It confirms that the logic base die has become a genuine competitive battleground.
And it lands in a market where AI demand has turned high-bandwidth memory into one of the scarcest resources in computing. Three things are worth watching next: whether a supply contract follows the qualification, when 16-high stacks ramp to volume, and how much of the 2027 and 2028 capacity wave actually reaches consumers.
